1. Field of Invention
The invention relates to a multi-chip package and, in particular, to a multi-chip package having a transparent substrate.
2. Related Art
As an electrical system increases its functionality and at the same time becomes more compact, conventional IC package and PCB (printed circuit board) assembling technologies are no longer able to satisfy the need for reducing the system size. As a result, an obvious trend is to integrate multiple complex functions in a single IC chip.
Conventional IC fabrication technology, however, utilizes variant sets of processes to fabricate IC chips having different functions. For example, processes for a logic IC are very different from those for a memory IC. Therefore, it is difficult to integrate a logic IC and a memory IC in one single IC chip, and still maintain adequate performance. Consequently, a new technique for packaging different chips into a single package known to those skilled in the art as a multi-chip package (MCP) is disclosed.
As multi-chip package technology develops, the IC chips in a single package can perform powerful functions, such that they can already be considered as a system. Such a package having multiple chips with a system level function is known as a system in package (SIP).
Presently, there are a variety of multi-chip package types, and different manufacturing methods thereof. Two types of multi-chip packages will be described hereinbelow to illustrate the structures and disadvantages thereof.
In the first case, a multi-chip package employing a lead frame to carry IC chips is described. With reference to FIG. 1, a conventional multi-chip package 1 includes a lead frame 11, at least two IC chips 13, a plurality of wires 15, and a molding compound 17. Each IC chip 13 is attached to the lead frame 11. The wires 15 respectively bond the IC chips 13 to leads or fingers of the lead frame 11. The molding compound 17 encapsulates the lead frame 11, IC chips 13 and wires 15. In the multi-chip package 1, each IC chip 13 is interconnected to the leads or fingers of the lead frame 15. In more detail, the wires 15 bond each IC chip 13 to the lead frame 11, so that the IC chips 13 can interconnect to each other via the leads or fingers of the lead frame 11. People skilled in the art should know that processes for manufacturing the multi-chip package 1 are similar to processes for manufacturing a conventional single-chip package. The lead frame 11, however, has limitation due to the conventional manufacturing technology, and it is difficult to manufacture a lead frame having fine pattern. Therefore, the lead frame is poorly suited for high pin-count chips. Moreover, since the lead frame 11 is a single layer structure, the leads or fingers of the lead frame 11 cannot cross over each other. As a result, the complexity and flexibility of the layout that the leads or the fingers can provide is restricted. To solve the previously mentioned problem, additional wires can be used to bond one lead or finger to another for connecting the leads or fingers as desired. However, this may make manufacturing processes more complex, and the size of the multi-chip package 1 may be further enlarged.
In the second case, another multi-chip package employing a BGA (Ball Grid Array) substrate to carry IC chips is described. With reference to FIG. 2, an additional multi-chip package 2 includes a BGA substrate 21, at least two IC chips 23, a plurality of wires 25, and a molding compound 27. The BGA substrate 21 is composed of a usual resin material. A plurality of fingers and trace lines are formed on the upper surface of the BGA substrate 21, and a plurality of solder balls 211 are formed on the bottom of the BGA substrate 21. Each IC chip 23 is mounted on the upper surface of the BGA substrate 21. The wires 25 bond the IC chips 23 to the fingers of the BGA substrate 21, respectively. The molding compound 27 encapsulates the BGA substrate 21, IC chips 23, and wires 25. In the multi-chip package 2, the IC chips 23 are interconnected to each other through the fingers and trace lines of the BGA substrate 21. In more detail, the wires 25 bond each IC chip 23 to the fingers of the BGA substrate 21, so that the IC chips 23 can interconnect to each other via the trace lines, which connect to the fingers. Each IC chip 23 can then electrically connect to external devices through the fingers, trace lines, and solder balls. People skilled in the art should know that the BGA substrate 21 has a plurality of conductive layers for forming the trace lines, so that a complex circuitry and the fine pattern can be provided between the IC chips. Furthermore, the IC chips 23 can be attached to the BGA substrate 21 by way of a flip-chip attachment (not shown). Thus, the wires 25 can be eliminated. In such a case, the manufacturing process of the multi-chip package 2 is simplified, and the size of the multi-chip package 2 is efficiently controlled. However, the BGA substrate has a higher production cost. In addition, the BGA substrate 21 composed of resin material has a thermal expansion coefficient higher than that of each IC chip 23, which is made of silicon. Thus, when the IC chips 23 are attached to the BGA substrate 21 by way of a flip-chip attachment, the reliability of the multi-chip package 2 may be degraded accordingly.
Moreover, since the insulating property of the BGA substrate 21 is limited, high frequency signals transmitted in the fingers and trace lines may decay easily due to parasitic capacitance and parasitic leakage resistance.
In summary, since the conventional multi-chip package usually employs a lead frame or a BGA substrate to carry IC chips and provide circuits for connecting each IC chip, the conventional multi-chip package does not provide fine pattern (as in the case of the lead frame), or requires a higher production cost (as in the case of the BGA substrate). In addition, the conventional multi-chip package, especially for the case of using the BGA technology, still has the problems of high-frequency signal decay and degraded reliability. Thus, it is an important objective of the invention to solve the previously mentioned problems when employing the lead frame or BGA substrate.
In view of the above-mentioned problems, an objective of the invention is to provide a multi-chip package, which has a circuit of fine pattern.
It is another objective of the invention to provide a multi-chip package, which efficiently reduces high frequency signal decay caused by parasitic capacitance and parasitic leakage resistance.
It is a further objective of the invention to provide a multi-chip package, which prevents degraded reliability due to the difference between the thermal expansion coefficients of the materials inside the multi-chip package.
To achieve the above-mentioned objectives, a multi-chip package includes a transparent substrate, at least two chips, a plurality of connecting terminals, and a molding compound. In the invention, the transparent substrate has a conductive layer for electrical inter-connection. The chips are mounted on the transparent substrate, wherein at least one of the chips is provided on the transparent substrate by way of a flip-chip attachment. The chips and the conductive layer form a circuitry system. The connecting terminals electrically connect to the circuitry system through a plurality of wires, so that the circuitry system can electrically connect to external devices through the wires and connecting terminals. The molding compound at least encapsulates the wires.
Since the multi-chip package of the invention employs the transparent substrate, such as a glass substrate, to carry the chips, the conductive layer with fine pattern can be formed on the transparent substrate by utilizing existing manufacturing technology. Moreover, the transparent substrate, especially the glass substrate, has a good insulation property and a low dielectric constant, so that high frequency signal decay caused by parasitic capacitance and parasitic leakage resistance can be reduced efficiently. Furthermore, since the glass substrate and the semiconductor chip have very similar thermal expansion coefficients, the reliability issue caused by the difference between the thermal expansion coefficients of the materials can be avoided.